Methods of forming an IC product comprising transistor devices with different threshold voltage levels
US11315835B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jun 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.