Hong Yu
44Patents
2h-index
47Co-inventors
57Inventor score
Filing activity: Dec 12, 2003 → Sep 4, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10192746B1 | STI inner spacer to mitigate SDB loading | Electricity | 4 | Active |
| US7006178B2 | One drop fill LCD panel having light-shielding pattern with first and second metal patterns | Physics | 3 | Expired |
| US11127842B2 | Single fin structures | Electricity | 2 | Active |
| US11037821B2 | Multiple patterning with self-alignment provided by spacers | Electricity | 2 | Active |
| US11888031B2 | Fin-based lateral bipolar junction transistor and method | Electricity | 1 | Active |
| US10971583B2 | Gate cut isolation including air gap, integrated circuit including same and related method | Electricity | 1 | Active |
| US11843044B2 | Bipolar transistor structure on semiconductor fin and methods to form same | Electricity | 1 | Active |
| US11705508B2 | Single fin structures | Electricity | 1 | Active |
| US11101364B2 | Field-effect transistors with diffusion blocking spacer sections | Electricity | 0 | Active |
| US11205648B2 | IC structure with single active region having different doping profile than set of active regions | Electricity | 0 | Active |
| US11264504B2 | Active and dummy fin structures | Electricity | 0 | Active |
| US11749727B2 | Bipolar junction transistors with duplicated terminals | Electricity | 0 | Active |
| US11810951B2 | Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials | Electricity | 0 | Active |
| US12389627B2 | Silicon germanium fins and integration methods | Electricity | 0 | Active |
| US12433014B2 | Structure having different gate dielectric widths in different regions of substrate | Electricity | 0 | Active |
| US12389616B2 | Transistors with multiple silicide layers | Electricity | 0 | Active |
| US11804541B2 | Bipolar transistor structure with emitter/collector contact to doped semiconductor well and related methods | Electricity | 0 | Active |
| US12261215B2 | Fin on silicon-on-insulator | Electricity | 0 | Active |
| US11923417B2 | Lateral bipolar junction transistors with a back-gate | Electricity | 0 | Active |
| US11315835B2 | Methods of forming an IC product comprising transistor devices with different threshold voltage levels | Electricity | 0 | Active |
| US11769806B2 | Bipolar junction transistors including wrap-around emitter and collector contacts | Electricity | 0 | Active |
| US12349374B2 | Lateral bipolar transistors | Electricity | 0 | Active |
| US11195761B2 | IC structure with short channel gate structure having shorter gate height than long channel gate structure | Electricity | 0 | Active |
| US11037937B2 | SRAM bit cells formed with dummy structures | Electricity | 0 | Active |
| US11004953B2 | Mask-free methods of forming structures in a semiconductor device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.