Scan wrapper architecture for system-on-chip
US11320485B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.