Differential reference voltage buffer
US11320846B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2018 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45138
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.