Executing an atomic primitive in a multi-core processor system
US11321146B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2019 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Feb 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.