Inventor · Cold Spring, NY, US

Michael Fee

93Patents
7h-index
61Co-inventors
75Inventor score

Filing activity: Mar 25, 1998 → May 24, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9104581B2 eDRAM refresh in a high performance cache architecture Physics 29 Active
US6516393B1 Dynamic serialization of memory access in a multi-processor system Physics 27 Expired
US8032716B2 System, method and computer program product for providing a new quiesce state Physics 20 Active
US6151655A Computer system deadlock request resolution using timed pulses Physics 17 Expired
US6073182A Method of resolving deadlocks between competing requests in a multiprocessor using global hang pulse logic Physics 15 Expired
US9104583B2 On demand allocation of cache buffer slots Physics 11 Active
US9477613B2 Position-based replacement policy for address synonym management in shared caches Physics 9 Active
US7739538B2 Double data rate chaining for synchronous DDR interfaces Physics 7 Active
US8244972B2 Optimizing EDRAM refresh rates in a high performance cache architecture Physics 6 Active
US11010210B2 Controller address contention assumption Physics 6 Active
US9104513B1 Managing quiesce requests in a multi-processor environment Physics 4 Active
US9507660B2 Eliminate corrupted portions of cache during runtime Physics 4 Active
US6219758A False exception for cancelled delayed requests Physics 4 Expired
US7574548B2 Dynamic data transfer control method and apparatus for shared SMP computer systems Physics 4 Active
US9703661B2 Eliminate corrupted portions of cache during runtime Physics 3 Active
US9858190B2 Maintaining order with parallel access data streams Physics 3 Active
US8250243B2 Diagnostic data collection and storage put-away station in a multiprocessor system Physics 3 Active
US8566532B2 Management of multipurpose command queues in a multilevel cache hierarchy Physics 3 Active
US9594689B2 Designated cache data backup during system operation Physics 3 Active
US8495287B2 Clock-based debugging for embedded dynamic random access memory element in a processor core Physics 3 Active
US7752475B2 Late data launch for a double data rate elastic interface Physics 2 Active
US9734110B2 Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing Physics 2 Active
US8352687B2 Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy Physics 2 Active
US9898407B2 Configuration based cache coherency protocol selection Physics 2 Active
US8560767B2 Optimizing EDRAM refresh rates in a high performance cache architecture Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.