Techniques to improve translation lookaside buffer reach by leveraging idle resources
US11321241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 10, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.