Compute in memory system
US11322195B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Sep 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.