Single-rail memory circuit with row-specific voltage supply lines and boost circuits
US11322200B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Dec 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.