Patent · US Active

Semiconductor structure formation

US11322388B2 · kind B2 · utility

0Cited by

3References

12Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Vivek Yadav · Boise, US
Shen Hu · Boise, US
Kangle Li · Boise, US
Sanjeev Sapra · Boise, US

Key dates

Filing date	Aug 23, 2019
Grant date	May 3, 2022
Priority date	—
Expiry date	Nov 6, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10B12/053
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.