Etch stop layer for semiconductor devices
US11322396B2 · kind B2 · utility
1Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.