Chip package and method of forming the same
US11322450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2018 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a semiconductor die, an insulating encapsulant, and a first redistribution layer is provided. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is provided over the semiconductor die and the encapsulant and includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion. The first redistribution portion is between the second redistribution portion and the semiconductor die. The first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion. The plurality of first conductive features electrically connects the semiconductor die to the second redistribution portion. The second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features. A top surface of the second dielectric portion is substantially level with top surfaces of the plurality of second conductive features. A method of forming the chip package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.