Film structure for bond pad
US11322464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Jan 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/05432
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.