Metal layer patterning for minimizing mechanical stress in integrated circuit packages
US11322465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Jun 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.