Alexander L. Barr
22Patents
10h-index
36Co-inventors
71Inventor score
Filing activity: Jan 18, 2002 → Jun 9, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6838322B2 | Method for forming a double-gated semiconductor device | Electricity | 176 | Expired |
| US7226833B2 | Semiconductor device structure and method therefor | Electricity | 122 | Expired |
| US6831350B1 | Semiconductor structure with different lattice constant materials and method for forming the same | Electricity | 78 | Expired |
| US6713381B2 | Method of forming semiconductor device including interconnect barrier layers | Electricity | 73 | Expired |
| US7018901B1 | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain | Electricity | 65 | Expired |
| US7282402B2 | Method of making a dual strained channel semiconductor device | Electricity | 42 | Expired |
| US7067868B2 | Double gate device having a heterojunction source/drain and strained channel | Electricity | 28 | Expired |
| US7037795B1 | Low RC product transistors in SOI semiconductor process | Electricity | 19 | Expired |
| US7205210B2 | Semiconductor structure having strained semiconductor and method therefor | Electricity | 13 | Expired |
| US7029980B2 | Method of manufacturing SOI template layer | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7208357B2 | Template layer formation | Emerging Cross-Sectional Technologies | 9 | Expired |
| US7045432B2 | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) | Electricity | 7 | Expired |
| US7163903B2 | Method for making a semiconductor structure using silicon germanium | Emerging Cross-Sectional Technologies | 5 | Expired |
| US7160769B2 | Channel orientation to enhance transistor performance | Electricity | 4 | Expired |
| US10586865B2 | Dual gate metal-oxide-semiconductor field-effect transistor | Electricity | 4 | Active |
| US7241647B2 | Graded semiconductor layer | Electricity | 3 | Expired |
| US7781840B2 | Semiconductor device structure | Electricity | 3 | Active |
| US6964911B2 | Method for forming a semiconductor device having isolation regions | Electricity | 3 | Expired |
| US7056778B2 | Semiconductor layer formation | Emerging Cross-Sectional Technologies | 2 | Expired |
| US7811382B2 | Method for forming a semiconductor structure having a strained silicon layer | Electricity | 1 | Active |
| US7927956B2 | Method for making a semiconductor structure using silicon germanium | Emerging Cross-Sectional Technologies | 0 | Active |
| US11322465B2 | Metal layer patterning for minimizing mechanical stress in integrated circuit packages | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.