Hybrid bonding technology for stacking integrated circuits
US11322481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2020 |
| Grant date | May 3, 2022 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.