Patent · US Active

Low current line termination structure

US11323108B1 · kind B1 · utility

0Cited by

1References

16Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Bob W. Verbruggen · Saggart, IE
Christophe Erdmann · Nice, FR
Ionut C. Cical · Dublin, IE

Key dates

Filing date	Nov 30, 2020
Grant date	May 3, 2022
Priority date	—
Expiry date	Nov 30, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH05K1/0246
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.