Predicting die susceptible to early lifetime failure
US11328108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2021 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.