Chip-stacked semiconductor package and method of manufacturing same
US11328966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Aug 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.