Semiconductor memory devices having contact plugs
US11329050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
Abstract
A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.