FinFET gate structure
US11329160B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 16, 2017 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.