Field-effect transistor and method for fabricating the same
US11329161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | May 10, 2022 |
| Priority date | — |
| Expiry date | Jun 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.