Oscillator circuit with negative resistance margin testing

US11329608B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mihail Jefremow · Augsburg, DE
• Rex Kho · Holzkirchen, DE
• Ralph Mueller-Eschenbach · Munich, DE
• Juergen Schaefer · Oberhaching, DE
• Arndt Voigtlaender · Ottobrunn, DE
• Wei Wang · Beijing, CN

Key dates

• Filing date: Oct 23, 2020
• Grant date: May 10, 2022
• Expiry date: Oct 23, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03B2200/0064
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Systems, methods, and circuits are provided for facilitating negative resistance margin testing in an oscillator circuit. An example oscillator circuit includes amplifier circuitry configured to be coupled in parallel with a resonator and variable resistance circuitry configured to, in response to a resistance control signal, adjust a resistance of the oscillator circuit.