Continuous adaptive data capture optimization for interface circuits
US11334509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Oct 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data interface circuit wherein calibration adjustments for data bit capture are made without disturbing normal system operation, is described. A plurality of DLL capture and delay circuits for sampling a trained optimal sampling point as well as leading and trailing sampling points are defined. A first stream of data bits is input to the data interface circuit and using a first calibration method, a first optimal sampling point for sampling the data bits input is established. A second stream of data bits is input to the data interface circuit during normal system operation. A second calibration method is performed that is different from the first, the second calibration method being performed whereby: at least one reference data path is established for sampling transition edges of the second stream of data bits input to the data interface during normal system operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.