Patent assignee · US · COMPANY

Uniquify, Inc.

24Patents
24Active
24Granted
54Portfolio score

Filing activity: Jun 6, 2008 → Jun 13, 2023 · 1 expiring within 5 years

Most-cited patents

PatentTitleAreaCited byStatus
US7975164B2 DDR memory controller Physics 23 Active
US8661285B2 Dynamically calibrated DDR memory controller Physics 13 Active
US8947140B2 Continuous adaptive training for data interface timing calibration Electricity 7 Active
US8990607B2 Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes Physics 4 Active
US9425778B2 Continuous adaptive data capture optimization for interface circuits Electricity 3 Active
US8941423B2 Method for operating a circuit including a timing calibration function Electricity 2 Active
US8843778B2 Dynamically calibrated DDR memory controller Physics 2 Active
US9805784B2 Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers Physics 1 Active
US9431091B2 Multiple gating modes and half-frequency dynamic calibration for DDR memory controllers Physics 1 Active
US9552853B2 Methods for calibrating a read data path for a memory interface Physics 1 Active
US9021293B2 Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes Physics 1 Active
US9898433B2 Continuous adaptive data capture optimization for interface circuits Electricity 1 Active
US12014767B2 Double data rate (DDR) memory controller apparatus and method Physics 1 Active
US8941422B2 Method for operating a data interface circuit where a calibration controller controls both a mission path and a reference path Electricity 0 Active
US12019573B2 Continuous adaptive data capture optimization for interface circuits Electricity 0 Active
US9075543B2 Method of application memory preservation for dynamic calibration of memory interfaces Physics 0 Active
US11334509B2 Continuous adaptive data capture optimization for interface circuits Electricity 0 Active
US11710516B2 Double data rate (DDR) memory controller apparatus and method Physics 0 Active
US9100027B2 Data interface circuit for capturing received data bits including continuous calibration Electricity 0 Active
US11348632B2 Double data rate (DDR) memory controller apparatus and method Physics 0 Active
US9300443B2 Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling Electricity 0 Active
US11714769B2 Continuous adaptive data capture optimization for interface circuits Electricity 0 Active
US9584309B2 Circuit for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling Electricity 0 Active
US9081516B2 Application memory preservation for dynamic calibration of memory interfaces Physics 0 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.