Memory device for performing program verify operation and method of operating the same
US11335406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of cell strings, a peripheral circuit, and control logic. Each of the cell strings includes a drain select transistor, a source select transistor, and a plurality of memory cells that are coupled in series between the drain select transistor and the source select transistor. The peripheral circuit may be configured to perform a program operation and a program verify operation on a cell string that is selected from among the plurality of cell strings. The control logic may be configured to control the peripheral circuit to boost a channel voltage of at least one unselected cell string, among the plurality of cell strings, based on a comparison between a degree of progress of the program operation and a reference degree of progress during the program verify operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.