Semiconductor structure and manufacturing method thereof
US11335672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2020 |
| Grant date | May 17, 2022 |
| Priority date | — |
| Expiry date | Jul 23, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.