Method and system for fabrication of a vertical fin-based field effect transistor

US11335810B2 · kind B2 · utility

Assignee

• Nexgen Power Systems, Inc. · US

Inventors

• Clifford Drowley · Santa Clara, US
• Ray Milano · Santa Clara, US
• Subhash Srinivas Pidaparthi · Santa Clara, US
• Andrew P. Edwards · San Jose, US
• Hao Cui · Gresham, US
• Shahin Sharifzadeh · Menlo Park, US

Key dates

• Filing date: Jul 15, 2020
• Grant date: May 17, 2022
• Expiry date: Jul 15, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/64

Abstract

A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.