Apparatus and method for controlling allocation of instructions into an instruction cache storage
US11340901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.