Managing open blocks in memory systems
US11340980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Oct 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a memory system includes a memory and a memory controller. The memory includes multiple blocks each having a plurality of word lines. The memory controller is coupled to the memory and configured to: evaluate a read disturbance level of an open block, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.