Patent · US Active

Secure logical-to-physical caching

US11341050B2 · kind B2 · utility

1Cited by

3References

20Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Zoltan Szubbocsev · Haimhausen, DE
Alberto Troia · Munich, DE
Federico Tiziani · Muggiò, IT
Antonino Mondello · Messina, IT

Key dates

Filing date	Jun 29, 2020
Grant date	May 24, 2022
Priority date	—
Expiry date	Jun 29, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/7201
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.