Cache for artificial intelligence processor
US11341066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Dec 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a cache including a dataflow controller for transmitting first data to a first processor and receiving second data from the first processor, an external direct memory access (DMA) controller for receiving the first data from an external memory to transmit the first data to the dataflow controller and receiving the second data from the dataflow controller to transmit the second data to the external memory, a scratchpad memory for storing the first data or the second data transmitted between the dataflow controller and the external DMA controller, a compression/decompression device for compressing data to be transmitted from the scratchpad memory to the external memory and decompressing data transmitted from the external memory to the scratchpad memory, and a transfer state buffer for storing transfer state information associated with data transfer between the dataflow controller and the external DMA controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.