Semiconductor package
US11342239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2019 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Apr 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.