Synchronization of clock signals generated using output dividers
US11342926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2021 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.