Flexible header alteration in network devices
US11343358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Jul 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/4641
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
At least a packet header of a packet received by a network device is provided to a programmable header alteration engine that includes a hardware input processor implemented in hardware and a programmable header alteration processor configured to execute computer readable instructions stored in a program memory. The hardware input processor determines whether the packet header is to be provided to a processing path coupled to the programmable header alteration processor or to be diverted to a bypass path that bypasses the programmable header alteration processor, and the packet header is provided to the processing path or to the bypass path based on the determination. The packet header is selectively i) processed by the programmable header alteration processor when the packet header is provided to the processing path and ii) not processed by the programmable header alteration processor when the packet header is provided to the bypass path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.