Packet aggregation and disaggregation method
US11343360B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides packet aggregation and disaggregation methods. In the packet aggregation methods, the protocol-independent packet processor (P4) switch stores plural message headers of plural packets in the ring buffer. When the plural message headers stored in the ring buffer reach a pre-defined amount of data, the P4 switch replaces the first flag header in the current packet with a second flag header so as to form a work packet. The egress pipeline of the P4 switch recirculates the work packet repeatedly, whenever it receives a work packet, a message header is extracted from a plurality of message headers in the ring buffer and added to the working packet for packet aggregation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.