Jun Li
20Patents
6h-index
72Co-inventors
72Inventor score
Filing activity: May 11, 2001 → Jul 8, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7073140B1 | Method and system for performing crosstalk analysis | Physics | 189 | Expired |
| US7549134B1 | Method and system for performing crosstalk analysis | Physics | 187 | Active |
| US9286524B1 | Multi-task deep convolutional neural networks for efficient and robust traffic lane detection | Physics | 71 | Active |
| US7243320B2 | Stochastic analysis process optimization for integrated circuit design and manufacture | Physics | 24 | Expired |
| US6721929B2 | High accuracy timing model for integrated circuit verification | Physics | 23 | Expired |
| US8005660B2 | Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture | Emerging Cross-Sectional Technologies | 9 | Active |
| US10156335B1 | Light-emitting device | Electricity | 5 | Active |
| US11991854B2 | Wireless charging base | Physics | 0 | Active |
| US12364067B2 | Semiconductor device | Electricity | 0 | Active |
| US11343360B2 | Packet aggregation and disaggregation method | Emerging Cross-Sectional Technologies | 0 | Active |
| US11967516B2 | Substrate support for chucking of mask for deposition processes | Electricity | 0 | Active |
| US8050294B2 | Method and system for transmitting in TDM mode | Electricity | 0 | Active |
| US12151810B2 | Tailstock type vertical take-off and landing unmanned aerial vehicle and control method thereof | Performing Operations; Transporting | 0 | Active |
| US11784112B2 | Integrated circuit package and method to manufacture the integrated circuit package to reduce bond wire defects in the integrated circuit package | Electricity | 0 | Active |
| US11190628B2 | High-speed data-plane packet aggregation and disaggregation method | Electricity | 0 | Active |
| US11923275B2 | Lead-frame assembly, semiconductor package and methods for improved adhesion | Electricity | 0 | Active |
| US11309439B2 | Package structure for semiconductor device, and semiconductor device | Electricity | 0 | Active |
| US11852669B2 | Online analysis system and method for line loss of transmission line | Physics | 0 | Active |
| US10217700B1 | Lead frame for integrated circuit device having J-leads and Gull Wing leads | Electricity | 0 | Active |
| US10847449B2 | Lead frame with selective patterned plating | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.