Imaging systems and methods for performing pixel binning and variable integration for analog domain regional feature extraction
US11343454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | May 24, 2022 |
| Priority date | — |
| Expiry date | Apr 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.