Patent · US Active

Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication

US11347828B2 · kind B2 · utility

0Cited by

1References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Biji George · Bengaluru, IN
Om Ji Omer · Bengaluru, IN
Dipan Kumar Mandal · Kanchinakote, IN
Cormac Brick · Dublin, IE
Lance Hacking · Spanish Fork, US
Sreenivas Subramoney · Bengaluru, IN
Belliappa Kuttanna · Austin, US

Key dates

Filing date	Mar 27, 2020
Grant date	May 31, 2022
Priority date	—
Expiry date	Mar 27, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F17/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A disclosed apparatus to multiply matrices includes a compute engine. The compute engine includes multipliers in a two dimensional array that has a plurality of array locations defined by columns and rows. The apparatus also includes a plurality of adders in columns. A broadcast interconnect between a cache and the multipliers broadcasts a first set of operand data elements to multipliers in the rows of the array. A unicast interconnect unicasts a second set of operands between a data buffer and the multipliers. The multipliers multiply the operands to generate a plurality of outputs, and the adders add the outputs generated by the multipliers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.