Lance Hacking
29Patents
7h-index
67Co-inventors
72Inventor score
Filing activity: Aug 18, 1997 → Jan 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6014735A | Instruction set extension using prefixes | Physics | 104 | Expired |
| US6073210A | Synchronization of weakly ordered write combining operations using a fencing mechanism | Physics | 43 | Expired |
| US6978357B1 | Method and apparatus for performing cache segment flush and cache segment invalidation operations | Physics | 17 | Expired |
| US6289431A | Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries | Physics | 11 | Expired |
| US7315952B2 | Power state coordination between devices sharing power-managed resources | Emerging Cross-Sectional Technologies | 8 | Expired |
| US5946713A | Memory attribute palette | Physics | 7 | Expired |
| US7272741B2 | Hardware coordination of power management activities | Physics | 7 | Expired |
| US7360103B2 | P-state feedback to operating system with hardware coordination | Emerging Cross-Sectional Technologies | 6 | Expired |
| US9189439B2 | Interface logic for a multi-core system-on-a-chip (SoC) | Emerging Cross-Sectional Technologies | 6 | Active |
| US6862679B2 | Synchronization of load operations using load fence instruction in pre-serialization/post-serialization mode | Physics | 5 | Expired |
| US7676603B2 | Write combining protocol between processors and chipsets | Physics | 3 | Expired |
| US8392728B2 | Reducing idle leakage power in an IC | Emerging Cross-Sectional Technologies | 2 | Active |
| US8050177B2 | Interconnect bandwidth throttler | Emerging Cross-Sectional Technologies | 2 | Active |
| US7877619B2 | Power mode control method and circuitry | Physics | 2 | Active |
| US9372768B2 | Debug interface | Physics | 2 | Active |
| US9830954B2 | Method and system for dynamic power management of memories | Emerging Cross-Sectional Technologies | 1 | Active |
| US8650629B2 | Interface logic for a multi-core system-on-a-chip (SoC) | Emerging Cross-Sectional Technologies | 1 | Active |
| US7284118B2 | Method and apparatus for synchronizing load operations | Physics | 1 | Expired |
| US8656411B2 | Technique for monitoring activity within an integrated circuit | Physics | 1 | Active |
| US8312309B2 | Technique for promoting determinism among multiple clock domains | Physics | 1 | Active |
| US11714998B2 | Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bits | Physics | 1 | Active |
| US11347828B2 | Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication | Physics | 0 | Active |
| US8412855B2 | Write combining protocol between processors and chipsets | Physics | 0 | Active |
| US12288153B2 | Schedule-aware tensor distribution module | Physics | 0 | Active |
| US7249245B2 | Globally observing load operations prior to fence instruction and post-serialization modes | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.