Double data rate (DDR) memory controller apparatus and method
US11348632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jun 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment, a computer-implemented method is provided, comprising the act of: configuring code or hardware to cause at least part of the hardware to operate as a double data rate (DDR) memory controller and to: produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of: at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.