Apparatus and method for managing program operation time and write latency in memory system
US11348646B2 · kind B2 · utility
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Key dates
| Filing date | Jul 2, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jul 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method of a memory system may include monitoring the size of a programmable area included in each of a plurality of open blocks in which a plurality of data having different attributes are stored, respectively, and generating a first free block by performing a first erase operation on a part of a plurality of erase target blocks based on the number of first open blocks, each open block of which the programmable area has a size less than a threshold value, among the plurality of open blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.