Memory device and method of operating the same
US11348647B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Dec 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a first string including a plurality of first memory cells, and a first select transistor connected between a first conductive line and the plurality of first memory cells; a second string including a plurality of second memory cells, and a second select transistor connected between the first conductive line and the plurality of second memory cells; a peripheral circuit configured to perform an erase operation of the first and second strings; and control logic. The control logic is configured to control the peripheral circuit to, during the erase operation, apply a first erase voltage to the first conductive line, float a first select line connected to the first select transistor after the first erase voltage is applied, and float a second select line connected to the second select transistor after the first select line is floated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.