Air spacer and method of forming same
US11349014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | May 31, 2022 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.