Column redundancy data architecture for yield improvement
US11354209B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Apr 13, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Jul 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.