Successive bit-ordered binary-weighted multiplier-accumulator
US11354383B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 19, 2019 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Nov 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.