Multi-level magnetic tunnel junction NOR device with wrap-around gate electrodes and methods for forming the same

US11355551B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Han-Jong Chia · Hsinchu, TW
• Bo-Feng Young · Taipei, TW
• Sai-Hooi Yeong · Hengshan, TW
• Chenchen Jacob Wang · Shanghai, CN
• Meng-Han Lin · Hsinchu, TW
• Yu-Ming Lin · Hsinchu, TW

Key dates

• Filing date: Jun 23, 2020
• Grant date: Jun 7, 2022
• Expiry date: Jun 23, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80

Abstract

A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.