Sense lines in three-dimensional memory arrays, and methods of forming the same
US11355554B2 · kind B2 · utility
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Key dates
| Filing date | May 8, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example apparatus includes a three-dimensional (3D) memory array including a sense line and a plurality of vertical stacks. Each respective on of the vertical stacks includes a different respective portion of the sense line, a first memory cell coupled to that portion of the sense line, a second memory cell coupled to that portion of the sense line, a first access line coupled to the first memory cell and a second access line coupled to the second memory cell. The first and second access lines are perpendicular to the sense line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.