Low parasitic Ccb heterojunction bipolar transistor
US11355618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Dec 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/824
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.