Chip package and manufacturing method thereof
US11355659B2 · kind B2 · utility
0Cited by
3References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Jun 7, 2022 |
| Priority date | — |
| Expiry date | Oct 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/933
Abstract
A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.